Three-Dimensional Vertically Interconnected Structure and Fabricating Method Thereof

ABSTRACT

The present invention discloses a three-dimensional vertically interconnected structure and a fabricating method for the same. The structure comprises at least two layers of chips which are stacked in sequence or stacked together face to face, and an adhesive material is used for adhesion between adjacent layers of said chips, each layer of chips contains a substrate layer and a dielectric layer sequentially bottom to top; an front surface of the chip has a first concave with an annular cross section, and the first concave is filled with metal inside to form a first electrical conductive ring connecting to microelectronic devices inside the chip via a redistribution layer; a first through layers of chips hole having the same radius and center as inner ring of the first electrical conductive ring penetrates the stacked chips and has a first micro electrical conductive pole inside that is electrically connected to the first electrical conductive ring. The three-dimensional vertically interconnected structure of the present invention enhances the strength of the electric interconnection and the adhesion between adjacent layers of chips, and in the meantime the disclosed fabricating method simplifies the process difficulty and therefore improves the yield.

FIELD OF THE INVENTION

The present invention relates to fields of semiconductors andmicro-sensor manufacture, and more particularly, to a three-dimensionalvertically interconnected structure and a fabricating method thereof.

BACKGROUND OF THE INVENTION

A Through-Silicon-Via (TSV) enabled 3D integration technology canprovide a high packaging density which enables more microelectronicdevices to be contained per unit volume, a shorter signal path to reduceparasitic capacitances, an increased operation frequency for the chips,etc. and thus attracts many attentions from academic and industrialcircles. However, the three-dimensionally stacked chips with TSVinterconnection still face challenges from several aspects such as TSVfabrication, TSV insulation, TSV filling with copper electroplating,temporary bonding of ultra-thin wafers, etc., of which those fromaspects such as micro-solder balls or bonding pad fabricating as well aslow temperature bonding thereof, thermal managing for stacked chips, andsignal managing between vertically adjacent chips inside the stacks areparticularly notable. The electrical interconnection and physicalconnection between the vertically adjacent chips in the stacks require abonding that is based on micro-solder balls or bonding pads for carryingout. On one hand, the TSV enabled 3D integration technology requiresdownscaling of micro-solder balls or bonding pads to maintain itstechnological advantages, with a typical size of the micro-solder ballsor bonding pads scaling down from hundreds micrometers to tensmicrometers even to several micrometers. On the other hand, the TSVenabled 3D integration technology depends on micro-solder balls orbonding pads to achieve a reliable electrical interconnection and aphysical connection, while scaling down of the micro-ball or bondingpads is less favorable for reliable electrical and physical connection.In addition, the increase in the number of stacked layers requires atleast one or more times of bonding and reflow processes to implement thebonding between vertically adjacent chips of the stacks. In this case,the micro-solder balls or bonding pads having completed one time ofbonding need to go through another bonding and another reflow processesto implement a multi-layered stack, which would cause damages to themicro-solder balls or bonding pads having already been bonded, andinfluence the reliability.

Moreover, the power dissipation per unit volume has a rise with anincrease of the number of the stacked layers. When the heat releasedfrom the chips inside the stacks increases, it is liable to generatehotspots inside the stacks, which results in a performance degradationof the stacked chips. This brings severe threat to the reliability ofthe stacks.

The TSV enabled 3D integration technology desires thickness of eachlayer of the chips in the stack keep declining, which shortens a signalpath between vertically adjacent chips inside the stacks, and enhancesthe performance of the stacked chips as well as the package density.However, when the thickness of the chips located in the stacksdecreases, the signals transmission across the surfaces of thevertically adjacent chips in the stacks may be interfered with eachother, which is not favorable for the chip stacks to function normally.

SUMMARY OF THE INVENTION 1. Technical Problem to be Solved

The technical problem to be solved by the present invention is how toenhance the strength of the electric interconnection and the bondingstrength between adjacent layers of chips in the three-dimensionalinterconnected stack in the fabricating of microelectronic devices, inorder to increase yield.

2. Technical Solution

In order to solve the above-mentioned problems, a three-dimensionalvertically interconnected structure is proposed, it comprises at leasttwo layers of chips which are stacked face to back or face to face (faceindicates the side with active devices on the chip, and back indicatesthe opposite side. For convenience of description, the surface of chipor wafer with active devices is also named as the front surface of thechip or wafer, the opposite surface is named as the backside surface.),and between the adjacent layers of chips there's a layer of adhesivematerial used for implementing an adhesion; each layer of chips in thevertically interconnected structure has a device layer on the substrateand a dielectric layer, sequentially from bottom to top, and a firstconcave with an annular cross section that embedded into the chip fromthe dielectric layer to the device layer or deeper into the substrate,and the first concave is filled with metal inside to form a firstelectrical conductive ring which is connected to microelectronic devicesinside the layer of chip via a redistribution layer atop the dielectriclayer; a first through layers of chips hole located at the inner of thefirst conductive ring on each layer and having the same radius andcenter as the inner ring of the first conductive ring penetrates thelayers of chips in the three dimensional vertically interconnectedstructure and has a first micro electrical conductive pole inside.

Preferably, on the front side and/or the back side of each layer ofchip(s), there are/is a first thermal conductive ring and a thermalconductive layer, the thermal conductive ring with an annularcross-section is embedded into each layer of chip and connected with thethermal conductive layer; a second through layers of chips hole locatedat the inner area of the first thermal conductive ring on each layer andhaving the same radius and center as the inner ring of the first thermalconductive ring penetrates the stacked layers of chips in the threedimensional vertically interconnected structure and has a first thermalconductive pole inside.

Preferably, on the front side and/or the back side of each layer of chipthere's a second concave with an annular cross section, and the secondconcave is filled with metal inside to form a second electricalconductive ring; the front side and/or the back side are/is coated witha patterned grounding conductive layer, and the second electricalconductive ring is connected with the grounding conductive layer; athird through layers of chips hole located at the inner area of thesecond concave and having the same radius and center as the inner ringof the second electrical conductive ring penetrates the stacked layersof chips in the three dimensional vertically interconnected structureand has a second micro electrical conductive pole inside.

Preferably, the adhesive material between adjacent layers of chips inthree dimensional vertically interconnected structure has micro-fluidchannels inside, and the micro-fluid channel contains a fourth throughhole vertically penetrating the whole layers of chips.

Preferably, the adhesive material is organics or metallic solders,wherein the organic adhesive material includes polyimide, epoxy resin,ultraviolet ray adhesive tape, dibenzo cyclobutene, non-conductiveadhesive, silicon rubber or p-Xylene, and the metallic solders includecopper, tungsten, gold, silver, tin, indium, nickel, palladium,copper-tin alloy, tin-silver-copper alloy, tin-silver alloy, gold-tinalloy, indium-gold alloy, lead-tin alloy, nickel-palladium alloy,nickel-gold alloy or nickel-palladium-gold alloy.

Preferably, the depth of the first concave is in a range from 1 μm to 30μm.

Preferably, the thermal conductive layer is of metallic thermalconductive material including gold, copper or aluminum.

Preferably, the grounding conductive layer is of metallic material orconductive paste, wherein the metallic material is gold, copper oraluminum.

Preferably, the first through layers of chips hole, the second throughlayers of chips hole and/or the third through layers of chips holehave/has a shape of cylinder, prism, cone or pyramid.

The present invention further provides a method for fabricating athree-dimensional vertically interconnected structure, which comprisesthe steps as follows:

S1, conducting a lithography on the surface of a single layer of siliconwafer or chip which has or has not undergone a thinning process to formmask for the first concave, then sequentially etching the dielectriclayer, device layer and a substrate layer of the single layer of waferor chip to form a first concave of fergitun-shape;

S2, depositing a barrier layer and a seed layer to cover an inside wallof the first concave, and then conducting copper electroplating to fillthe first concave, for forming a first electrical conductive ring;

S3, forming a redistribution layer which connects the first electricalconductive ring with microelectronic devices inside the layer of waferor chip, wherein the redistribution layer comprises a dielectric layerand a metallic interconnection layer;

S4, etching the dielectric layer of the redistribution layer, thedielectric layer, device layer and substrate of the wafer or chipsequentially to form a first through hole inside the first electricalconductive ring, wherein the first through hole has the same crosssection shape as/the identical center to that of the inner ring of thefirst electrical conductive ring;

S5, aligning the layers of wafers or chips which have completed stepsS1-S4 and stacking them with adhesive bonding sequentially; the firstthrough holes of each layers is aligned and forms a through layers ofchips hole;

S6, depositing a seed layer and electroplating on one side of themultiple stacked layers of wafers or chips to seal the through layers ofchips hole; and the electroplated metallic layer functions as a seedlayer for following electroplating; filling the through layers of chipsholes which penetrate the multi-layered stack from bottom to top withelectroplating to form a first micro electrical conductive pole, andremoving the seed layer and electroplated metallic layer, for finishingthe fabricating of a three-dimensional vertically interconnectedstructure.

Preferably, in step S2, depositing an insulation layer to cover theinside wall of the first concave, before depositing the barrier layerand the seed layer, wherein the insulation layer is selected as Sillicaor polyimide, and a method of sputtering or plasma enhanced chemicalvapor deposition is used for depositing the insulation layer.

Preferably, after step S2, repeating steps S1-S2 to form a secondelectrical conductive electrical ring and/or a thermal conductive ringhaving the similar shape as the first electrical conductive ring on thefront surface and/or the backside surface of the single layer of waferor chip.

Preferably, in step S3, forming a grounding electrical conductive layerand/or a thermal conductive layer on the front surface and/or thebackside surface of the single layer of wafer or chip, wherein thegrounding electrical conductive layer is connected with the secondelectrical conductive ring, and the thermal conductive layer isconnected with the thermal conductive ring.

Preferably, in step S5, patterning the layer of adhesive material toform micro-fluid channels for heat dissipation.

The present invention further provides a method for fabricating athree-dimensional vertically interconnected structure, which comprisesthe steps as follows:

S1, conducting a lithography on the front surface of a single layer ofsilicon wafer or chip to form mask for the first concave, thensequentially etching a dielectric layer, the device layer and thesubstrate of the single layer of wafer or chip to form a first concaveof fergitun-shape;

S2, depositing a barrier layer and a seed layer to cover an inside wallof the first concave, and conducting copper electroplating to fill thefirst concave, for forming a first electrical conductive ring;

S3, forming a redistribution layer which connects the first electricalconductive ring with microelectronic devices inside the layer of waferor chip, wherein the redistribution layer comprises a dielectric layerand a metallic interconnection layer;

S4, sequentially etching the dielectric layer of the redistributionlayer, the dielectric layer and the substrate of the layer of wafer orchip to form a blind hole inside the first electrical conductive ring,which has the same radius and center as the inner ring of the firstelectrical conductive ring;

S5, stacking two layers of wafers or chips which have completed stepsS1-S4 face-to-face and aligning the same, wherein the wafers or chipsare adhered to each other by using organics or metallic solders;

S6, conducting a thinning process on both sides of the stacked layers ofwafers or chips until the blind hole is exposed to implement a throughhole;

S7, stacking the layers of wafers or chips which have completed stepsS1-S4 on the stacked layers of wafers or chips which have completedsteps S1-S6, or stacking the stacked layers of wafers or chips whichhave completed steps S1-S6 and aligning the same, wherein the stackedlayers of wafers or chips and the layers of wafer are adhered togetherwith organics or metallic solders; and then repeating step S6 toimplement a stacking of three or more layers of wafers or chips with athrough layers of chips hole;

S8, depositing a seed layer and conducting electroplating on one side ofmulti-layered, stacked wafers or chips to seal the through hole; and theelectroplated layer functions as seed layer for followingelectroplating; filling the through layers of wafers or chips holeswhich penetrate the multi-layered, stacked wafers or chips from bottomto top with electroplating to form a micro electrical conductive pole,and removing the seed layer and electroplated metallic layer, forfinishing a fabrication of a three-dimensional vertically interconnectedstructure.

Preferably, in step S3, forming a second electrical conductive ringand/or a thermal conductive ring on the front surface and/or thebackside surface of the single layer of wafer or chip.

Preferably, in step S3, forming a grounding electrical conductive layerand/or a thermal conductive layer on the front surface and/or thebackside surface of the single layer of wafer or chip, wherein thegrounding electrical conductive layer is connected with the secondelectrical conductive ring, and the thermal conductive layer isconnected with the thermal conductive ring.

Preferably, in step S5, patterning the adhesive material to formmicro-fluid channels for heat dissipation.

Preferably, after step S4, depositing an insulation layer to cover asidewall and a bottom of the blind hole, and conducting etching at anopening of the blind hole to remove the insulation layer inside theelectrical conductive ring and expose the inside wall of the firstelectrical conductive ring.

3. Beneficial Effects

Compared with traditional TSV-based three-dimensional integrationtechnologies, the present invention has implemented an adhesion betweenadjacent layers of wafers or chips and an electric interconnectionbetween different layer of wafers or chips via different structures.Organic materials and solders are applied to implement the adhesionbetween adjacent layers of wafers or chips only, but not the electricinterconnection between different layers of wafers or chips; thereforeflexible bonding, welding and adhesive bonding technologies for wafersmay be used. The electrical conductive ring that surrounds a microelectrical conductive pole internally penetrating the stacked wafers orchips implements an electric interconnection between wafers and anelectric interconnection between microelectronic devices inside thewafers or chips, with simple process and high reliability. The designsof micro-fluid channels and thermal conductive layers between verticallyadjacent wafers or chips in the stacks can effectively relieve a heataccumulation of chips in the stacks. The design of grounding metalliclayers between vertically adjacent wafers or chips in the stacks caneffectively relieve a signal crosstalk between chips in the stacks.After finishing an adhesion between adjacent layers of wafers or chips,a micro electrical conductive pole which internally penetrates throughlayers of wafers or chips hole of the stack is formed in a singleprocess step, which implements an electric interconnection betweendifferent layers of wafers or chips of a three-dimensional verticallyinterconnected structure. Therefore, the difficulty in the fillingprocess is reduced, the processing time is shortened and the rate offinished, electroplated products is increased.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 (a)-(b) are a top view and a cross-sectional schematic viewrespectively illustrating that a fergitun-shaped concave is formed onthe front surface of a single layer of wafer or chip in athree-dimensional vertical interconnection method according to anembodiment of the present invention.

FIG. 2 is a cross-sectional schematic view illustrating that anelectrical conductive ring is formed in the front surface of a singlelayer of wafer or chip in a three-dimensional vertical interconnectionmethod according to an embodiment of the present invention.

FIG. 3 is a cross-sectional schematic view illustrating a state where aredistribution layer is formed on the font surface of a single layer ofwafer or chip in a three-dimensional vertical interconnection methodaccording to an embodiment of the present invention.

FIG. 4 is a cross-sectional schematic view illustrating that a TSV isformed inside an electrical conductive ring of the front surface of asingle layer of wafer or chip and the sidewall is insulated in afabricating method for a three-dimensional vertically interconnectedstructure according to in an embodiment of the present invention.

FIG. 5 is a cross-sectional schematic view illustrating that two layersof wafers which have completed an interconnection are aligned andadhered together in a three-dimensional vertical interconnection methodaccording to an embodiment of the present invention.

FIG. 6 is a cross-sectional schematic view illustrating that two layersof wafers which have completed an interconnection are aligned, adhered,and electroplated for filling to implement a vertical interconnection ina three-dimensional vertical interconnection method according to anembodiment of the present invention.

FIG. 7 is a cross-sectional schematic view illustrating that two layersof wafers which have completed an interconnection are aligned front tofront and adhered in a three-dimensional vertical interconnection methodaccording to an embodiment of the present invention.

FIG. 8 is a cross-sectional schematic view illustrating that two layersof wafers which have completed an interconnection are aligned front tofront, adhered and thinned on both sides of the wafer to implement athrough layers of wafer or chip hole with TSVs on each layers of waferor chip being vertically aligned in a three-dimensional verticalinterconnection method according to an embodiment of the presentinvention.

FIG. 9 is a cross-sectional schematic view illustrating that anotherlayer of wafers is stacked above a pair of wafers which have completedan interconnection and are adhered face to face, and that the anotherlayer of wafers is conducted a thinning process on the backside thereofin a three-dimensional vertical interconnection method according to anembodiment of the present invention.

FIG. 10 is a cross-sectional schematic view illustrating that two layersof wafers which have completed an interconnection are aligned, adhered,and the through layers of wafers or chips hole is filled withelectroplating to implement a vertical interconnection in athree-dimensional vertical interconnection method according to anembodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The embodiments of the present invention are further described below inconjunction with drawings and examples. The following embodiments areintended to describe the present invention, but not to limit the scopeof the present invention.

The First Embodiment

With reference to FIG. 1-FIG. 7, the first embodiment of the presentinvention provides a three-dimensional vertically interconnectedstructure, it comprises at least two layers of wafers or chips which arestacked in sequence or stacked together face-to-face and a layer ofadhesive material 040 is used for adhesion between different layers ofwafers or chips; each layer of wafers or chips contains a substratelayer 010 and a dielectric layer 011 sequentially from bottom to top; anupper surface of the wafer or chip has a fergitun-shaped concave 020whose cross-section is of annular shape, and the concave 020 is filledwith metal inside to form an electrical conductive ring 022 whichconnects to microelectronic devices inside the wafer or chip via aredistribution layer 012; a TSV 030, having the same inner diameter andthe identical center with that of the electrical conductive ring 022,penetrates the stacked wafers or chips and is provided with a microelectrical conductive pole inside.

Preferably, the layer of adhesive material 040 between adjacent layersof wafers or chips has micro-fluid channels inside, and the micro-fluidchannel contains through holes vertically penetrating said stackedwafers or chips.

The Second Embodiment

The second embodiment of the present invention provides athree-dimensional vertically interconnected structure, it comprises atleast two layers of wafers or chips which are stacked in sequence orstacked together face-to-face, and a layer of adhesive material 040 isused for an adhesion between adjacent layers of wafers or chips; eachlayer of wafers or chips contains a substrate layer 010 and a surfacedielectric layer 011 sequentially from bottom to top; an upper surfaceof the wafer or chip has a fergitun-shaped concave 020 whosecross-section is of annular shape, and the concave 020 is filled withmetal inside to form an electrical conductive ring 022 which connects tomicroelectronic devices inside the wafer or chip via a redistributionlayer 012; a through layers of wafer or chip hole 030, having the sameinner diameter and the identical center with that of the electricalconductive ring 022, penetrates the stacked wafers or chips and isprovided with a micro electrical conductive pole inside.

A front surface and/or a backside surface of each layer of wafers orchips have/has a thermal conductive ring, a front surface and/or abackside surface of the wafer or chip have/has a thermal conductivelayer, and the thermal conductive layer is connected with the thermalconductive ring; a through layers of wafer or chip hole, having the sameinner diameter and the identical center with that of the thermalconductive ring, penetrates the stacked wafers or chips and is providedwith a micro thermal conductive pole inside.

Preferably, the layer of adhesive material 040 between adjacent layersof wafers or chips has micro-fluid channels inside which contain throughlayers of wafer or chips holes, and said through layers of wafer orchips holes vertically penetrate said stacked wafers or chips.

The Third Embodiment

The third embodiment of the present invention provides athree-dimensional vertically interconnected structure, it comprises atleast two layers of wafers or chips which are stacked in sequence orstacked together face-to-face, and a layer of adhesive material 040 isused for adhesion between adjacent layers of wafers or chips; each layerof wafers or chips contains a substrate layer 010 and a dielectric layer011 sequentially from bottom to top; a front surface of the wafer orchip has a fergitun-shaped concave 020 whose cross-section is of annularshape, and the concave 020 is filled with metal inside to form anelectrical conductive ring 022 which connects to microelectronic devicesinside the wafer or chip via a redistribution layer 012; a throughlayers of wafers or chips hole 030, having the same inner diameter andthe identical center with that of the electrical conductive ring 022,penetrates the stacked wafers or chips and is provided with a microelectrical conductive pole inside.

A front surface and/or a backside surface of the wafer or chip have/hasa concave 020 whose cross-section is of annular shape, and the concave020 is filled with metal to form a conductive ring 022; the backsidesurface (of the wafer or chip) is coated with a grounding conductivelayer, and the conductive ring is connected with the groundingconductive layer; a through layers of wafers or chips hole 030, havingthe same inner diameter and the identical center with that of theconductive ring, penetrates said stacked wafers or chips and is providedwith a micro electrical conductive pole 033 inside.

Preferably, the layer of adhesive material 040 between different layersof wafers or chips has micro-fluid channels inside, and the micro-fluidchannel contains through holes vertically penetrating said stackedwafers or chips.

The Fourth Embodiment

The fourth embodiment of the present invention provides athree-dimensional vertically interconnected structure, it comprises atleast two layers of wafers or chips which are stacked together back toface or face-to-face, and a layer of adhesive material 040 is used foran adhesion between adjacent layers of wafers or chips; each layer ofwafers or chips contains a substrate layer populated with electricdevices and a dielectric layer 011, sequentially from bottom to top; thefront surface of the wafer or chip has a fergitun-shaped concave 020whose cross-section is of annular shape, and the concave 020 is filledwith metal inside to form an electrical conductive ring 022 whichconnects to microelectronic devices inside the wafer or chip via aredistribution layer 012; a through layers of wafers or chips hole 030,having the same inner diameter and the identical center with that of theelectrical conductive ring 022, penetrates the stacked wafers or chipsand is provided with a micro electrical conductive pole inside.

A front surface and/or a backside surface of each layer of wafers orchips have/has a thermal conductive ring, an front surface and/or abackside surface of the wafer or chip have/has a thermal conductivelayer, and the thermal conductive layer is connected with the thermalconductive ring; a through layers of wafers or chips hole, having thesame inner diameter and the identical center with that of the thermalconductive ring, penetrates the stacked wafers or chips and is providedwith a micro thermal conductive pole inside.

A front surface and/or a backside surface of the wafer or chip have/hasa concave 020 whose cross-section is of annular shape, and the concave020 is filled with metal inside to form an electrical conductive ring022; the backside surface (of the wafer or chip) is coated with agrounding electrical conductive layer, and the electrical conductivering is connected with the grounding electrical conductive layer; athrough layers of wafers or chips hole 030, having the same innerdiameter and the identical center with that of the electrical conductivering, penetrates said stacked wafers or chips and is provided with amicro electrical conductive pole 033 inside.

The layer of adhesive material 040 between adjacent layers of wafers orchips has micro-fluid channels inside, and the micro-fluid channelcontains through layers of wafers or chips holes vertically penetratingsaid stacked wafers or chips.

The adhesive material in each of the above-mentioned examples may beselected as organics or metallic solders; wherein, the organics includespolyimide, epoxy resin, ultraviolet ray adhesive tape, dibenzocyclobutene, non-conductive adhesive, silicon rubber or 2 p-Xylene, andthe metallic solders include copper, tungsten, gold, silver, tin,indium, nickel, palladium, copper-tin alloy, tin-silver-copper alloy,tin-silver alloy, gold-tin alloy, indium-gold alloy, lead-tin alloy,nickel-palladium alloy, nickel-gold alloy or nickel-palladium-goldalloy.

The fabricating method for the above-mentioned three-dimensionalvertically interconnected structure may be implemented by two examplesas follows.

For convenience of descriptions, the front surface of the wafer whichhas completed fabrication of microelectronic devices indicates thesurface of the wafer populated with dielectric layer and devices and thebackside surface indicates a surface opposite to the front surface.

The Fifth Embodiment

A fabricating method for a three-dimensional vertically interconnectedstructure comprises the following steps:

Step A. conducting lithography on the front surface of a single layer ofsilicon wafer or chip which has completed the fabrication ofmicroelectronic devices therein to form annular patterns, and thensequentially etching a dielectric layer 011 and a substrate layer 010 ofthe single layer of wafer or chip to form a fergitun-shaped concave 020.FIG. 1 (a) and FIG. 1 (b) are respectively a top view and across-sectional view along the radial direction of the fergitun-shapedconcave 020. Etching of the dielectric layer 011 of the single layer ofwafer may be implemented with reactive ion etching (RIE) or other wetetching or dry etching techniques. The etching of the substrate layer010 of the wafer or chip may be implemented by applying deep reactiveetching (DRIE) or other wet etching or dry etching techniques. The depthof the concave 020 is preferably in a range from 1 μm to 30 μm. Thesingle layer of wafer or chip may be an ultra-thin one which has beenconducted a thinning process on the backside thereof.

Step B. depositing a barrier layer of TiW, and a seed layer of gold (Au)or copper (Cu) to cover the inside wall of the fergitun-shaped concave020; conducting lithography to form a photo-resists mask on the frontsurface of the wafer which exposes the concave region and an electrodecontacting area and covers the remaining areas of the wafers; conductingcopper electroplating to fill the fergitun-shaped concave 020. The metalfor filling the fergitun-shaped concave 020 forms a fergitun-shapedelectrical conductive ring 022, as shown in FIG. 2. The photo-resist,the barrier layer and the seed layer outside the fergitun-shaped concave020 are then removed, and the front surface can be planarized dependingon requirements. An insulation layer 021 (such as sillica, polyimide,etc.) can be deposited to cover an inside wall of the concave 020,before depositing the barrier layer and the seed layer. The depositionof the barrier layer and the seed layer can be implemented by applyingconventional processes in semiconductor industry, such as sputtering,evaporation, chemical vapor deposition (CVD), etc. The deposition ofmaterial for the insulation layer can be implemented by applyingconventional processes in semiconductor industry such as sputtering andplasma enhanced chemical vapor deposition (PECVD), etc.

Similarly, step A and step B can be repeated to form a fergitun-shapedconcave 020, a insulation layer 021 and an electrical conductive ring022 having the similar structures (with those have been described) onthe backside of a single layer of wafer or chip.

Step C. forming a redistribution layer 012 which connects the electricalconductive ring with microelectronic devices inside the wafer or chip,wherein an interconnecting wire 013 of the redistribution layer 012 canbe of metal such as copper, aluminum, etc., and can be also of othermetal. And the dielectric layer of the redistribution layer 012 may beof a material such as polyimide, BCB, epoxy resin, etc., and may be alsoof other dielectric materials. This step includes but not limited toformation of at least one redistribution layer 012.

This step may further include forming a grounding electrical conductivelayer or a thermal conductive layer on the front surface or a backsidesurface of a single layer of wafer or chip. The grounding electricalconductive layer is connected with an electrical conductive ring, andthe thermal conductive layer is connected with a thermal conductivering.

The grounding electrical conductive layer may be of a material such asgold, copper, aluminum, etc., and may be also of other conductivepastes.

The thermal conductive layer may be of a thermal conductive materialsuch as gold, copper, aluminum, etc., and may be also of other heatdissipation materials.

Step D. conducting lithography, and sequentially etching the dielectriclayer of the redistribution layer 012 and the dielectric layer 011 toform a Through-Silicon-Via 030 inside the electrical conductive ring022; The TSV 030 has the same radius and the center as the inner ring ofthe electric conductive ring. The forming of the TSV 030 may beimplemented by applying depth reactive ion etching (DRIE) technique orother technique such as laser drilling, etc. Under condition of DRIE,TSV 030 may be implemented by etching from one side or etching from oneside then the other. The etching for the dielectric layer 011 and thedielectric layer of the redistribution layer 012 may be implemented byapplying RIE or other wet or dry etching techniques. If the depth of asingle layer of wafer or chip exceeds a value of 300 μm, it's preferableto apply the double-sided etching, in order to increase the efficiency.An insulation layer 031 of conventional materials for insulation layersin semiconductor industry such as sillica may be deposited to cover thesidewall and the bottom of the TSV 030. Conducting etching at an openingof the TSV 030 of the wafer or chip to remove the insulation layer 031inside the electrical conductive ring 022 and expose the sidewall of theelectrical conductive ring 022.

Step E. aligning multi-layers of said single layer of wafer or chipwhich have completed steps A, B, C and D and stacking the same, as shownin FIG. 5. The vertically aligned TSVs of layers of wafers or chips formthrough layers of wafers or chips hole that penetrates the stackedwafers or chips. The vertically adjacent wafers or chips may be adheredby using an adhesive layer 040 of organics such as polyimide, BCB, epoxyresin, etc., or may be welded by using conventional welding solders suchas solders of Al—Ge, Au—Sn, Cu—Sn, etc.

This step may include a process of patterning the adhesive materiallayer 040, so that the wafers are bonded to form micro-fluid channelsfor heat dissipation.

The adhesive layer 040 in this step may be selected as organics ormetallic solders, wherein the organics includes polyimide, epoxy resin,ultraviolet ray adhesive tape, dibenzo cyclobutene, non-conductiveadhesive, silicon rubber or p-Xylene, and may be also selected asmetallic solders including but not limited to copper, tungsten, gold,silver, tin, indium, nickel, palladium, copper-tin alloy,tin-silver-copper alloy, tin-silver alloy, gold-tin alloy, indium-goldalloy, lead-tin alloy, nickel-palladium alloy, nickel-gold alloy ornickel-palladium-gold alloy. But not limit to this, other conventionalsolders in the semiconductor processing industry may be also used.

Step F. depositing a seed layer on one surface of the multi-stackedlayers of wafers or chips, and conducting copper electroplating, to sealthe through layers of wafers or chips holes constituted of verticallyaligned TSVs 030; filling the through layers of wafers or chips holefrom bottom to top with copper electroplating to form a micro electricalconductive pole 033; conducting electroplating with solder balls orbonding pads 050; removing the electroplated seed layer, for finishingthe fabrication of a three-dimensional vertically interconnectedstructure, as shown in FIG. 6.

The through layers of wafers or chips hole 030 of the stacks in thisstep may be also filled through copper electroplating with an assistancewafer. In particular, a seed layer is deposited on one surface of theassistance wafer and then the stacked wafers or chips is clamped to theassistance wafer. The through layers of wafers or chips hole 030 isfilled with copper electroplating from bottom to top to form a microelectrical conductive pole which penetrates the stacked wafers or chips.

The Sixth Embodiment

A method for fabricating a three-dimensional vertically interconnectedstructure comprises the following steps:

Step A. conducting lithography on the front surface of a single layer ofsilicon wafer or chip which has completed the fabrication ofmicroelectronic devices therein to form photo-resist masks for annularpatterns, and then sequentially etching the dielectric layer 011 and thesubstrate layer 010 of the single layer of wafer or chip to form afergitun-shaped concave 020. FIG. 1 (a) and FIG. 1 (b) are respectivelya top view and a cross-sectional view of the fergitun-shaped concave 020along the radial direction. Etching of the dielectric layer 011 may beimplemented by applying RIE or other wet or dry etching technologies.Etching of the substrate layer 010 may be implemented by applying DRIEor other wet or dry etching technologies. It's proposed that the depthof the concave is in a range from 1 μm to 30 μm. The single layer ofwafer or chip may be an ultra-thin one which has been conducted athinning process on the backside thereof.

Step B. depositing a barrier layer of TiW and a seed layer of gold (Au)or copper (Cu) to cover the sidewall and the bottom of thefergitun-shaped concave 020; conducting lithography to form aphoto-resists mask on the front surface of the wafer which exposes theconcave region and an electrode contacting area and covers the remainingareas of the wafers; conducting copper electroplating to fill thefergitun-shaped concave 020. The metal filled inside of thefergitun-shaped concave 020 forms a fergitun-shaped electricalconductive ring 022, as shown in FIG. 2. The photo-resist, the barrierlayer and the seed layer outside the concave are then removed, and thefront surface can be planarized depending on requirements. An insulationlayer 021 of a material such as sillica, polyimide, etc. can bedeposited to cover the wall of the concave 020, before depositing thebarrier layer and the seed layer. The deposition of the barrier layerand the seed layer can be implemented by applying conventional processesin semiconductor industry such as methods of sputtering, evaporation,chemical vapor deposition (CVD), etc. The deposition of materials forthe insulation layer can be implemented by applying conventionalprocesses in semiconductor industry such as sputtering, plasma enhancedchemical vapor deposition (PECVD), etc.

Step C. forming a redistribution layer 012 which connects the electricalconductive ring 022 with microelectronic devices inside the wafer orchip, wherein an interconnecting wire 013 of the redistribution layer012 can be of metal such as copper, aluminum, etc., and can be also ofother conductive materials. A dielectric layer of the redistributionlayer 012 may be of a material such as polyimide, BCB, epoxy resin,etc., and may be also of other dielectric materials. This step includesbut not limited to formation of at least one redistribution layer 012.As shown in FIG. 3.

Step D. conducting lithography, and sequentially etching the dielectriclayer 012 of the redistribution layer and the dielectric layer 011 ofthe wafer or chip to form a blind TSV 035 inside the electricalconductive ring 022; The blind TSV has the same radius and the center asthe inner ring of the electrical conductive ring 022. The forming of theblind TSV 035 may be implemented by applying drilling technologies suchas DRIE etching, laser drilling, etc. Under condition of etchingtechnology, etching of the dielectric layer 011 and the dielectric layerof the redistribution layer 012 may be implemented by applying RIE orother wet or dry etching technologies. Etching of the substrate layer010 of the wafer or chip may be implemented by applying DRIE etchingtechnology. A material for an insulation layer such as sillica may bedeposited to cover the sidewall and the bottom of the blind TSV 035 forinsulation thereof. Conducting etching at an opening of the blind TSV035 to remove the insulation layer inside the electrical conductive ringand expose the sidewall of the electrical conductive ring 022.

Step E. as shown in FIG. 7, aligning two layers of the single layer ofwafer or chip which have completed steps A-D face-to-face, and thewafers or chips are adhered to each other by an adhesive material. Theadhesive material 040 in this step may be selected as organics ormetallic solders, wherein the organics includes polyimide, epoxy resin,ultraviolet ray adhesive tape, ibenzo cyclobutene, non-conductiveadhesive, silicon rubber or p-Xylene, and may be also selected asmetallic solders including but not limited to copper, tungsten, gold,silver, tin, indium, nickel, palladium, copper-tin alloy,tin-silver-copper alloy, tin-silver alloy, gold-tin alloy, indium-goldalloy, lead-tin alloy, nickel-palladium alloy, nickel-gold alloy ornickel-palladium-gold alloy. But not limited to this, other conventionalsolders in semiconductor processing industry may be also used.

This step may include a process of patterning the adhesive material 040,to form micro-fluid channels for heat dissipation.

Step F. conducting a thinning process on two sides of the two layers ofwafers or chips which have completed a stacking, until exposing theblind TSVs 030 on both surfaces of the stacked wafers to implement athrough layers of wafers or chips hole, as shown in FIG. 8. The thinningprocess may be implemented by applying chemically mechanical polishing(CMP) or other wet or dry thinning technologies.

Step G. stacking another single layer of wafer which has completed stepsA-D with those layers of wafers or chips having completed steps A-F, andthen repeating steps E and F to implementing a stacking of three or morelayers of wafers or chips. As shown in FIG. 9.

Step H. depositing a seed layer and conducting electroplating on oneside of multi-stacked wafers or chips to seal the through layers ofwafers or chips holes constituted of vertically aligned TSVs; fillingthe through layers of wafers or chips hole from bottom to top withcopper electroplating to form a micro electrical conductive pole;conducting tin electroplating to form solder balls or bonding pads 050;removing the seed layer, for finishing the fabrication of athree-dimensional vertically interconnected structure, as shown in FIG.10.

The through layers of wafers or chips hole 030 of the stacks in thisstep may be also filled through copper electroplating with an assistancewafer. In particular, a seed layer is deposited on one surface of theassistance wafer and then the stacked wafers or chips is clamped to theassistance wafer. The through layers of wafers or chips hole 030 isfilled with copper electroplating from bottom to top to form a microelectrical conductive pole which penetrates the stacked wafers or chips

It can be seen from the above-mentioned examples that, compared withtraditional TSV based three-dimensional integration technologies, thepresent invention has implemented an adhesion between adjacent layers ofwafers or chips and an electric interconnection between wafers or chipsthrough different structures. Organic materials and solders are appliedto implement the adhesion between but not the electric interconnectionbetween different layers of wafers or chips, therefore flexible bonding,welding and adhesive technologies for wafers may be used. The electricalconductive ring that surrounds a micro electrical conductive poleinternally penetrating the stacked wafers or chips implements anelectric interconnection between wafers and an electric interconnectionbetween microelectronic devices inside the wafers or chips, with simpleprocess and high reliability. The designs for micro-fluid channels andthermal conductive layers between vertically adjacent wafers or chips instacks can effectively relieve heat accumulation of chips in stacks. Thedesigns of micro-fluid channels and thermal conductive layers betweenvertically adjacent wafers or chips in the stacks can effectivelyrelieve a heat accumulation of chips in the stacks. The design ofgrounding metallic layers between vertically adjacent wafers or chips inthe stacks can effectively relieve a signal crosstalk between chips inthe stacks. After finishing an adhesion between multi-layered wafers andchips, a micro electrical conductive pole which internally penetratesthe TSV of the stacks is formed in a single process, which implements anelectric interconnection between different layers of wafers or chips ofa three-dimensional vertically interconnected structure. Therefore, thedifficulty in the filling process is reduced, the processing time isshortened and the rate of finished, electroplated products is increased.

The descriptions above are only preferred embodiments of the presentinvention. It should be pointed out that, for those skilled in the art,several modifications and variations may further be made withoutdeparting from technical principle, which should also be regarded asfalling into the scope of protection of the present invention.

INDUSTRIAL APPLICABILITY

The technical solution of the present invention has the followingadvantages: it implements an adhesion between adjacent layers of wafersor chips and an electric interconnection between wafers or chips viadifferent structures. Organic materials and solders are applied toimplement the adhesion but not the electric interconnection betweendifferent layers of wafers or chips, therefore flexible bonding, weldingand adhesive bonding technologies for wafers may be used. A conductivering that surrounds a micro electrical conductive pole internallypenetrating the stacked wafers or chips implements an electricinterconnection between different layers of wafers through the microelectrical conductive pole and an electric interconnection betweenmicroelectronic devices inside the wafers or chips, with simple processand high reliability. The designs of micro-fluid channels and thermalconductive layers between vertically adjacent wafers or chips in thestacks can effectively relieve a heat accumulation of chips in thestacks. The design of grounding metallic layers between verticallyadjacent wafers or chips in the stacks can effectively relieve a signalcrosstalk between chips in the stacks. After finishing an adhesionbetween multi-layered wafers and chips, a micro electrical conductivepole which internally penetrates TSV through holes of the stacks isformed in a single process, which implements an electric interconnectionbetween different layers of wafers or chips of a three-dimensionalvertically interconnected structure. Therefore, the difficulty in thefilling process is reduced, the processing time is shortened and therate of finished, electroplated products is increased.

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 10. A fabricating method for a three-dimensional vertically interconnected structure, characterized by comprising steps of: S1, conducting lithography on the surface of a single layer of silicon wafer or chip which has or has not undergone a thinning process to form photo-resist mask for annular patterns, then sequentially etching a dielectric layer and a substrate layer of the single layer of wafer or chip to form a first concave of fergitun-shape; S2, depositing a barrier layer and a seed layer to cover an inside wall of the first concave, and then copper electroplating to fill the first concave, for forming a first electrical conductive ring; S3, forming a redistribution layer which connects the first electrical conductive ring with microelectronic devices inside the wafer or chip, wherein the redistribution layer comprises a dielectric layer and a metallic interconnection layer; S4, etching the dielectric layer of the redistribution layer and the dielectric layer of the wafer or chip sequentially to form a first through-silicon-via (TSV) inside the first electrical conductive ring, wherein the first TSV has the same radius and center as the inner ring of the first electrical conductive ring; S5, sequentially stacking single layers of wafers or chips which have completed steps S1-S4 and aligning the same, and adjacent wafers or chips being adhered to each other by using organics or metallic solders; S6, depositing a seed layer and electroplating copper on one side of the multi-stacked layers of wafers or chips to seal a first through layers of wafers or chips hole that is constituted of vertically aligned TSVs; filling the first through layers of wafers or chips holes which penetrate the multi-layered stacks from bottom to top with copper electroplating to form a first micro electrical conductive pole, and removing the electroplated copper and seed layer, for finishing the fabrication of the three-dimensional vertically interconnected structure.
 11. The fabricating method for the three-dimensional vertically interconnected structure of claim 10, characterized by, before depositing the barrier layer and the seed layer of step S2, depositing an insulation layer to cover the inside wall of the first concave, sillica or polyimide being selected as the insulation layer, and a method of sputtering or plasma enhanced chemical vapor deposition being used for depositing the insulation layer.
 12. The fabricating method for the three-dimensional vertically interconnected structure of claim 11, characterized by, after step S2, repeating steps S1-S2 to form a second electrical conductive ring and/or a thermal conductive ring having the same structure on a front surface of a layer of wafer or chip and/or a backside surface.
 13. The fabricating method for the three-dimensional vertically interconnected structure of claim 12, characterized by, in step S3, forming a grounding electrical conductive layer and/or a thermal conductive layer on a front surface of the layer of wafer or chip and/or a backside surface; the grounding electrical conductive layer is connected with the second electrical conductive ring, and the thermal conductive layer is connected with the thermal conductive ring.
 14. The fabricating method for the three-dimensional vertically interconnected structure of claim 10, characterized by, in step S5, patterning the adhesive material to form micro-fluid channels for heat dissipation.
 15. A fabricating method for a three-dimensional vertically interconnected structure, characterized by comprising steps of: S1, conducting lithography on a front surface of a single layer of silicon wafer or chip to form a photo-resist mask for annular patterns, then sequentially etching a dielectric layer and a substrate layer of the single layer of wafer or chip to form a first concave of fergitun-shape; S2, depositing a barrier layer and a seed layer to cover the inside wall of the first concave, and electroplating copper to fill the first concave, for forming a first electrical conductive ring; S3, forming a redistribution layer which connects the first electrical conductive ring with microelectronic devices inside the wafer or chip, wherein the redistribution layer comprises a dielectric layer and a metallic interconnection layer; S4, sequentially etching the dielectric layer of the redistribution layer and the dielectric layer of the wafer or chip to form a blind TSV inside the first electrical conductive ring, the blind TSV having the same radius and center as the inner ring of the first conductive ring; S5, stacking two layers of wafers or chips which have completed steps S1-S4 face-to-face and aligning the same, wherein the wafers or chips being adhered to each other by using organics or metallic solders; S6, conducting a thinning process on both sides of the layers of wafers or chips which are stacked until the blind TSVs of each layer of wafer or chip is exposed to implement a through layers of wafers or chips hole; S7, stacking a single layer of wafer or chip which has completed steps S1-S4 on the wafers or chips which have completed steps S1-S6, and adhering the same, and then repeating step S6 to implement a stacking of three or more layers of wafers or chips; S8, depositing a seed layer and conducting copper electroplating on one side of the stacked wafers or chips to seal the through layers of wafers or chips hole; filling the through layers of wafers or chips holes which penetrate the stacked wafers or chips from bottom to top with copper electroplating to form a micro electrical conductive pole, and removing the electroplated copper and the seed layer, for finishing the fabrication of the three-dimensional vertically interconnected structure.
 16. The fabricating method for the three-dimensional vertically interconnected structure of claim 15, characterized by, in step S3, forming a second conductive ring and/or a thermal conductive ring on an active region surface of the single layer of wafer or chip and/or a backside surface.
 17. The fabricating method for the three-dimensional vertically interconnected structure of claim 16, characterized by, in step S3, forming a grounding electrical conductive layer and/or a thermal conductive layer on a front surface and/or a backside surface of a layer of wafer or chip; the grounding electrical conductive layer is connected with the second electrical conductive ring, and the thermal conductive layer is connected with the thermal conductive ring.
 18. The fabricating method for the three-dimensional vertically interconnected structure of claim 15, characterized by, in step S5, patterning the adhesive material to form micro-fluid channels for heat dissipation.
 19. The fabricating method for the three-dimensional vertically interconnected structure of any one of claims 15-18, characterized by, after step S4, depositing an insulation layer to cover the inside wall of the blind TSV, and conducting etching at an opening of the blind hole, to remove the insulation layer inside the conductive ring and expose the sidewall of the first electrical conductive ring. 